Documents

  • 8815210

    Accepted author manuscript, 558 KB, PDF-document

DOI

Memristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big Data problems. The design of such architectures requires a radically new automatic design flow because the memristor is a passive device that uses resistance to encode its logic value. This paper proposes a design flow for mapping parallel algorithms on the CIM architecture. Algorithms with similar data flow graphs can be mapped on the crossbar using the same template containing scheduling, placement, and routing information; this template is named skeleton. By configuring such a skeleton with different
pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.
Original languageEnglish
Title of host publication2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
EditorsW. Zhao, C.A. Moritz
Place of PublicationNew York
PublisherAssociation for Computing Machinery (ACM)
Pages165-170
Number of pages6
ISBN (Electronic)978-1-4503-4330-5
ISBN (Print)978-1-4673-8927-3
DOIs
Publication statusPublished - 2016
Event2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China
Duration: 18 Jul 201620 Jul 2016

Conference

Conference2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated titleNANOARCH 2016
CountryChina
CityBeijing
Period18/07/1620/07/16

    Research areas

  • Skeleton, Memristors, Routing, Algorithm design and analysis, Computer architecture, Scheduling, Hardware

ID: 8815210