Abstract
Memristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big Data problems. The design of such architectures requires a radically new automatic design flow because the memristor is a passive device that uses resistance to encode its logic value. This paper proposes a design flow for mapping parallel algorithms on the CIM architecture. Algorithms with similar data flow graphs can be mapped on the crossbar using the same template containing scheduling, placement, and routing information; this template is named skeleton. By configuring such a skeleton with different
pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.
pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.
Original language | English |
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Title of host publication | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
Editors | W. Zhao, C.A. Moritz |
Place of Publication | New York |
Publisher | Association for Computing Machinery (ACM) |
Pages | 165-170 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-4503-4330-5 |
ISBN (Print) | 978-1-4673-8927-3 |
DOIs | |
Publication status | Published - 2016 |
Event | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016 |
Conference
Conference | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
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Abbreviated title | NANOARCH 2016 |
Country/Territory | China |
City | Beijing |
Period | 18/07/16 → 20/07/16 |
Bibliographical note
Accepted Author ManuscriptKeywords
- Skeleton
- Memristors
- Routing
- Algorithm design and analysis
- Computer architecture
- Scheduling
- Hardware