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DOI

Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory's address decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the address decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the address decoder logic. In particular, it reduces the degradation of the address decoder's setup delay by up to 43% with an execution overhead of only 1%.
Original languageEnglish
Title of host publication2019 IEEE Latin American Test Symposium (LATS)
Place of PublicationDanvers
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-7281-1756-0
ISBN (Print)978-1-7281-1757-7
DOIs
Publication statusPublished - 2019
Event20th IEEE Latin American Test Symposium, LATS 2019 - Santiago, Chile
Duration: 11 Mar 201913 Mar 2019

Conference

Conference20th IEEE Latin American Test Symposium, LATS 2019
CountryChile
CitySantiago
Period11/03/1913/03/19

    Research areas

  • address decoder, aging, memory, mitigation

ID: 54216817