Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
PublisherIEEE
Volume2020-April
ISBN (Electronic)9781728153599
DOIs
Publication statusPublished - 1 Apr 2020
Event38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States
Duration: 5 Apr 20208 Apr 2020

Conference

Conference38th IEEE VLSI Test Symposium, VTS 2020
CountryUnited States
CitySan Diego
Period5/04/208/04/20

ID: 73863097