TY - GEN
T1 - Special Session - Emerging Memristor Based Memory and CIM Architecture
T2 - 38th IEEE VLSI Test Symposium, VTS 2020
AU - Bishnoi, Rajendra
AU - Wu, Lizhou
AU - Fieback, Moritz
AU - Munch, Christopher
AU - Nair, Sarath Mohanachandran
AU - Tahoori, Mehdi
AU - Wang, Ying
AU - Li, Huawei
AU - Hamdioui, Said
PY - 2020/4/1
Y1 - 2020/4/1
N2 - Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.
AB - Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.
UR - http://www.scopus.com/inward/record.url?scp=85086500145&partnerID=8YFLogxK
U2 - 10.1109/VTS48691.2020.9107595
DO - 10.1109/VTS48691.2020.9107595
M3 - Conference contribution
VL - 2020-April
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
PB - IEEE
Y2 - 5 April 2020 through 8 April 2020
ER -