Abstract
Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.
Original language | English |
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Title of host publication | 49th European Solid-State Device Research Conference, ESSDERC 2019 |
Publisher | Editions Frontieres |
Pages | 98-101 |
Number of pages | 4 |
Volume | 2019-September |
ISBN (Electronic) | 9781728115399 |
DOIs | |
Publication status | Published - 1 Sept 2019 |
Event | 49th European Solid-State Device Research Conference, ESSDERC 2019 - Cracow, Poland Duration: 23 Sept 2019 → 26 Sept 2019 |
Conference
Conference | 49th European Solid-State Device Research Conference, ESSDERC 2019 |
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Country/Territory | Poland |
City | Cracow |
Period | 23/09/19 → 26/09/19 |