Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

Original languageEnglish
Title of host publication49th European Solid-State Device Research Conference, ESSDERC 2019
PublisherEditions Frontieres
Pages98-101
Number of pages4
Volume2019-September
ISBN (Electronic)9781728115399
DOIs
Publication statusPublished - 1 Sep 2019
Event49th European Solid-State Device Research Conference, ESSDERC 2019 - Cracow, Poland
Duration: 23 Sep 201926 Sep 2019

Conference

Conference49th European Solid-State Device Research Conference, ESSDERC 2019
CountryPoland
CityCracow
Period23/09/1926/09/19

ID: 67444047