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Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures. / T Hart, P. A.; Babaie, M.; Charbon, E.; Vladimirescu, A.; Sebastiano, F.

49th European Solid-State Device Research Conference, ESSDERC 2019. Vol. 2019-September Editions Frontieres, 2019. p. 98-101 8901745.

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Harvard

T Hart, PA, Babaie, M, Charbon, E, Vladimirescu, A & Sebastiano, F 2019, Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures. in 49th European Solid-State Device Research Conference, ESSDERC 2019. vol. 2019-September, 8901745, Editions Frontieres, pp. 98-101, 49th European Solid-State Device Research Conference, ESSDERC 2019, Cracow, Poland, 23/09/19. https://doi.org/10.1109/ESSDERC.2019.8901745

APA

T Hart, P. A., Babaie, M., Charbon, E., Vladimirescu, A., & Sebastiano, F. (2019). Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures. In 49th European Solid-State Device Research Conference, ESSDERC 2019 (Vol. 2019-September, pp. 98-101). [8901745] Editions Frontieres. https://doi.org/10.1109/ESSDERC.2019.8901745

Vancouver

T Hart PA, Babaie M, Charbon E, Vladimirescu A, Sebastiano F. Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures. In 49th European Solid-State Device Research Conference, ESSDERC 2019. Vol. 2019-September. Editions Frontieres. 2019. p. 98-101. 8901745 https://doi.org/10.1109/ESSDERC.2019.8901745

Author

T Hart, P. A. ; Babaie, M. ; Charbon, E. ; Vladimirescu, A. ; Sebastiano, F. / Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures. 49th European Solid-State Device Research Conference, ESSDERC 2019. Vol. 2019-September Editions Frontieres, 2019. pp. 98-101

BibTeX

@inproceedings{cc1115f783b24b2ea41c24ce02d2a338,
title = "Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures",
abstract = "Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.",
author = "{T Hart}, {P. A.} and M. Babaie and E. Charbon and A. Vladimirescu and F. Sebastiano",
year = "2019",
month = sep,
day = "1",
doi = "10.1109/ESSDERC.2019.8901745",
language = "English",
volume = "2019-September",
pages = "98--101",
booktitle = "49th European Solid-State Device Research Conference, ESSDERC 2019",
publisher = "Editions Frontieres",
note = "49th European Solid-State Device Research Conference, ESSDERC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",

}

RIS

TY - GEN

T1 - Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

AU - T Hart, P. A.

AU - Babaie, M.

AU - Charbon, E.

AU - Vladimirescu, A.

AU - Sebastiano, F.

PY - 2019/9/1

Y1 - 2019/9/1

N2 - Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

AB - Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

UR - http://www.scopus.com/inward/record.url?scp=85075723180&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2019.8901745

DO - 10.1109/ESSDERC.2019.8901745

M3 - Conference contribution

AN - SCOPUS:85075723180

VL - 2019-September

SP - 98

EP - 101

BT - 49th European Solid-State Device Research Conference, ESSDERC 2019

PB - Editions Frontieres

T2 - 49th European Solid-State Device Research Conference, ESSDERC 2019

Y2 - 23 September 2019 through 26 September 2019

ER -

ID: 67444047