Abstract
Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit which
generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor
crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.
generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor
crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.
Original language | English |
---|---|
Title of host publication | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
Editors | W. Zhao, C.A. Moritz |
Place of Publication | New York |
Publisher | Association for Computing Machinery (ACM) |
Pages | 43-48 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-4503-4330-5 |
DOIs | |
Publication status | Published - 2016 |
Event | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016 |
Conference
Conference | 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) |
---|---|
Abbreviated title | NANOARCH 2016 |
Country/Territory | China |
City | Beijing |
Period | 18/07/16 → 20/07/16 |
Keywords
- Memristors
- Hardware design languages
- Logic gates
- IP networks
- Radiation detectors
- Routing
- Wires