This paper proposes an array of nMOS based temperature sensors incorporated into a CMOS image sensor (CIS) for thermal compensation of the latter. Each temperature sensor features the same area as that of an image pixel. Both the temperature and the image sensors' outputs are read out by the column-level zoom ADCs, each of which offers 16 bits, with a 4-bit unit capacitor array (UCA) SAR and a 13-bit 2nd-order incremental delta-sigma ADC (DSADC) as the first and the second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. The column zoom ADC samples twice as fast while keeping its linearity, or, expands the dynamic range by 15 dB, for the image sensors, compared to a DSADC only alternative. To digitize the temperature sensor, the proposed zoom ADC is capable of quantization errors less than 16 µV, which is equivalent to a 0.125 0C resolution for a 130 µV/0C temperature coefficient. The proposed temperature sensor is simulated to keep its errors within ±0.21 0C upon 2nd-order curve fitting, with 3 sigma Monte Carlo inaccuracies less than ±0.74 0C, between 0 and 100 0C, at a power and an area of 144 µW and 121 µm2, respectively, with a sampling period of 64 µs.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
ISBN (Electronic)9781728103976
Publication statusPublished - 2019
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 26 May 201929 May 2019


Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019

    Research areas

  • ADC, Analog-to-digital converter, CMOS image sensor, Delta-sigma, SAR, Temperature sensor, Zoom ADC

ID: 62489545