Resistive RAM (RRAM) is one of the emerging nonvolatile memories that may not only replace DRAM and/or Flash in the future, but also enable new computing paradigms such as computation-in-memory. Providing high quality and efficient
test solutions are of great importance in order to enable the commercialization of such products. This paper discusses all aspects of RRAM testing including defects, fault models, test algorithms, Design-for-Testability (DFT) schemes, and future challenges. The paper highlights also the limitations and the inaccuracies of existing approaches and shows that using a linear resistor to model a defect in RRAM (as it is done today) is too pessimistic, and unable to represent the non-linear behavior of the defective RRAM devices. This may result in incorrect fault models, which in turn leads to low quality test solutions. The paper therefore also presents a novel defect modeling methodology that appropriately captures the non-linear RRAM behavior. To show its superiority, the methodology is applied to a forming defect and the results are compared with those of
traditional approach.
Original languageEnglish
Title of host publicationInternational Test Conference 2018 - Proceedings
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1-9
Number of pages9
ISBN (Electronic)978-1-5386-8382-8
DOIs
Publication statusPublished - 2018
EventITC 2018: International Test Conference - Phoenix Convention Center, Phoenix, AZ, United States
Duration: 29 Oct 20181 Nov 2018
http://www.itctestweek.org/

Conference

ConferenceITC 2018
CountryUnited States
CityPhoenix, AZ
Period29/10/181/11/18
OtherCo-located with ISTFA 2018
Internet address

    Research areas

  • RRAM, Test, DFT, Defect Model, Defect

ID: 47797086