The TM3270 media-processor data cache

JW van de Waerdt; S Vassiliadis; JP van Itegem; H van Antwerpen

doi:doi:10.1109/ICCD.2005.107

The TM3270 media-processor data cache

JW van de Waerdt, S Vassiliadis, JP van Itegem, H van Antwerpen

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

Abstract

This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.

Original language	Undefined/Unknown
Title of host publication	Computer design: VLSI in computers & processors, IICD 2005
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	334-341
Number of pages	8
ISBN (Print)	0-7695-2451-6
DOIs	https://doi.org/doi:10.1109/ICCD.2005.107
Publication status	Published - 2005
Event	IEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA - Piscataway Duration: 2 Oct 2005 → 5 Oct 2005

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA
Period	2/10/05 → 5/10/05

Bibliographical note

editors onbekend, sb

Keywords

conference contrib. refereed
Conf.proc. > 3 pag

Access to Document

doi:10.1109/ICCD.2005.107

Cite this

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title = "The TM3270 media-processor data cache",

abstract = "This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce {"}collapsed{"} and {"}twoslot{"} load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.",

keywords = "conference contrib. refereed, Conf.proc. > 3 pag",

author = "{van de Waerdt}, JW and S Vassiliadis and {van Itegem}, JP and {van Antwerpen}, H",

note = "editors onbekend, sb; IEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA ; Conference date: 02-10-2005 Through 05-10-2005",

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AU - van de Waerdt, JW

AU - Vassiliadis, S

AU - van Itegem, JP

AU - van Antwerpen, H

N1 - editors onbekend, sb

PY - 2005

Y1 - 2005

N2 - This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.

AB - This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

U2 - doi:10.1109/ICCD.2005.107

DO - doi:10.1109/ICCD.2005.107

M3 - Conference contribution

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EP - 341

BT - Computer design: VLSI in computers & processors, IICD 2005

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

T2 - IEEE iInternational conference of computer design (ICCD) 2005, San Jose, USA

Y2 - 2 October 2005 through 5 October 2005

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