Microelectronics industry is moving towards three dimensional stacking, packaging and integration of chips to answer to the need for increased functionality, miniaturization and cost reduction of smart systems. Their increasing complexity require novel and more robust approaches for the fabrication of vertical-interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane direction. However, due to significant technology difficulties and high production costs, existing 3D technologies have limited usages. This paper describes the development of a new and robust fabrication method for dense high-aspect-ratio conductive through-polymer-vias for three-dimensional stacking, packaging and heterogeneous integration of semiconductor dies and wafers. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy molding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial which was achieved by using foil assisted transfer molding technology. Even for very thin pillars with extreme aspect ratios of >15 clean connection surfaces are obtained. Advantages of this technology are: pillars are more easily exposed and wetted by the plating solution, faster metallization than bottom-up plating, no voiding nor trapping of plating chemicals, suitable for parallel fabrication, lithographically defined, enabling layout variations and extremely accurate positioning of the vias. The technology is promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging
Original languageEnglish
Title of host publication2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)
PublisherIEEE Society
Pages1-7
Number of pages7
ISBN (Electronic)978-1-4673-7269-5
DOIs
Publication statusPublished - Dec 2015
Event2015 IEEE 17th Electronics Packaging and Technology Conference - Singapore, Singapore
Duration: 2 Dec 20154 Dec 2015

Conference

Conference2015 IEEE 17th Electronics Packaging and Technology Conference
Abbreviated titleEPTC 2015
CountrySingapore
CitySingapore
Period2/12/154/12/15

    Research areas

  • Electrical conductive high-aspect-ratio vertical interconnect technology, 3D-Heterogeneous System Integration, foil assisted molding, Packaging, Through Polymer Via (TPV), metallization

ID: 10056896