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Through-polymer-via for 3D heterogeneous integration and packaging. / Hamelink, J.; Poelma, Rene; Kengen, M.

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC). IEEE Society, 2015. p. 1-7.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Hamelink, J, Poelma, R & Kengen, M 2015, Through-polymer-via for 3D heterogeneous integration and packaging. in 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC). IEEE Society, pp. 1-7, 2015 IEEE 17th Electronics Packaging and Technology Conference, Singapore, Singapore, 2/12/15. https://doi.org/10.1109/EPTC.2015.7412400

APA

Hamelink, J., Poelma, R., & Kengen, M. (2015). Through-polymer-via for 3D heterogeneous integration and packaging. In 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) (pp. 1-7). IEEE Society. https://doi.org/10.1109/EPTC.2015.7412400

Vancouver

Hamelink J, Poelma R, Kengen M. Through-polymer-via for 3D heterogeneous integration and packaging. In 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC). IEEE Society. 2015. p. 1-7 https://doi.org/10.1109/EPTC.2015.7412400

Author

Hamelink, J. ; Poelma, Rene ; Kengen, M. / Through-polymer-via for 3D heterogeneous integration and packaging. 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC). IEEE Society, 2015. pp. 1-7

BibTeX

@inproceedings{2764f71ab5a3406f88f432cc56e63922,
title = "Through-polymer-via for 3D heterogeneous integration and packaging",
abstract = "Microelectronics industry is moving towards three dimensional stacking, packaging and integration of chips to answer to the need for increased functionality, miniaturization and cost reduction of smart systems. Their increasing complexity require novel and more robust approaches for the fabrication of vertical-interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane direction. However, due to significant technology difficulties and high production costs, existing 3D technologies have limited usages. This paper describes the development of a new and robust fabrication method for dense high-aspect-ratio conductive through-polymer-vias for three-dimensional stacking, packaging and heterogeneous integration of semiconductor dies and wafers. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy molding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial which was achieved by using foil assisted transfer molding technology. Even for very thin pillars with extreme aspect ratios of >15 clean connection surfaces are obtained. Advantages of this technology are: pillars are more easily exposed and wetted by the plating solution, faster metallization than bottom-up plating, no voiding nor trapping of plating chemicals, suitable for parallel fabrication, lithographically defined, enabling layout variations and extremely accurate positioning of the vias. The technology is promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging",
keywords = "Electrical conductive high-aspect-ratio vertical interconnect technology, 3D-Heterogeneous System Integration, foil assisted molding, Packaging, Through Polymer Via (TPV), metallization",
author = "J. Hamelink and Rene Poelma and M. Kengen",
year = "2015",
month = "12",
doi = "10.1109/EPTC.2015.7412400",
language = "English",
pages = "1--7",
booktitle = "2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)",
publisher = "IEEE Society",

}

RIS

TY - GEN

T1 - Through-polymer-via for 3D heterogeneous integration and packaging

AU - Hamelink, J.

AU - Poelma, Rene

AU - Kengen, M.

PY - 2015/12

Y1 - 2015/12

N2 - Microelectronics industry is moving towards three dimensional stacking, packaging and integration of chips to answer to the need for increased functionality, miniaturization and cost reduction of smart systems. Their increasing complexity require novel and more robust approaches for the fabrication of vertical-interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane direction. However, due to significant technology difficulties and high production costs, existing 3D technologies have limited usages. This paper describes the development of a new and robust fabrication method for dense high-aspect-ratio conductive through-polymer-vias for three-dimensional stacking, packaging and heterogeneous integration of semiconductor dies and wafers. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy molding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial which was achieved by using foil assisted transfer molding technology. Even for very thin pillars with extreme aspect ratios of >15 clean connection surfaces are obtained. Advantages of this technology are: pillars are more easily exposed and wetted by the plating solution, faster metallization than bottom-up plating, no voiding nor trapping of plating chemicals, suitable for parallel fabrication, lithographically defined, enabling layout variations and extremely accurate positioning of the vias. The technology is promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging

AB - Microelectronics industry is moving towards three dimensional stacking, packaging and integration of chips to answer to the need for increased functionality, miniaturization and cost reduction of smart systems. Their increasing complexity require novel and more robust approaches for the fabrication of vertical-interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane direction. However, due to significant technology difficulties and high production costs, existing 3D technologies have limited usages. This paper describes the development of a new and robust fabrication method for dense high-aspect-ratio conductive through-polymer-vias for three-dimensional stacking, packaging and heterogeneous integration of semiconductor dies and wafers. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy molding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial which was achieved by using foil assisted transfer molding technology. Even for very thin pillars with extreme aspect ratios of >15 clean connection surfaces are obtained. Advantages of this technology are: pillars are more easily exposed and wetted by the plating solution, faster metallization than bottom-up plating, no voiding nor trapping of plating chemicals, suitable for parallel fabrication, lithographically defined, enabling layout variations and extremely accurate positioning of the vias. The technology is promising for low-cost, large-scale parallel fabrication of micro-vias for 3D heterogeneous integration and packaging

KW - Electrical conductive high-aspect-ratio vertical interconnect technology

KW - 3D-Heterogeneous System Integration

KW - foil assisted molding

KW - Packaging

KW - Through Polymer Via (TPV)

KW - metallization

U2 - 10.1109/EPTC.2015.7412400

DO - 10.1109/EPTC.2015.7412400

M3 - Conference contribution

SP - 1

EP - 7

BT - 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

PB - IEEE Society

ER -

ID: 10056896