Abstract
Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.
Original language | English |
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Title of host publication | 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Subtitle of host publication | Proceedings |
Publisher | IEEE |
Pages | 794-799 |
Number of pages | 6 |
ISBN (Electronic) | 978-3-98192632-3 |
ISBN (Print) | 978-1-7281-0331-0 |
DOIs | |
Publication status | Published - 2019 |
Event | DATE 2019 : Design, Automation and Test in Europe Conference and Exhibition - Florence, Italy Duration: 25 Mar 2019 → 29 Mar 2019 Conference number: 22nd |
Conference
Conference | DATE 2019 |
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Country/Territory | Italy |
City | Florence |
Period | 25/03/19 → 29/03/19 |
Keywords
- automata
- parallel processing
- time-devision multiplexing