Abstract
In recent years, computation is shifting from conventional high performance servers to Internet of Things (IoT) edge devices, most of which require the processing of cognitive tasks. Hence, a great effort is put in the realization of neural network (NN) edge devices and their efficiency in inferring a pretrained Neural Network. In this paper, we evaluate the retention issues of emerging resistive memories used as non-volatile weight storage for embedded NN. We exploit the asymmetric retention behavior of Spintronic based Magnetic Tunneling Junctions (MTJs), which is also present in other resistive memories like Phase-Change memory (PCM) and ReRAM, to optimize the retention of the NN accuracy over time. We propose mixed retention cell arrays and an adapted training scheme to achieve a trade-off between array size and the reliable long-term accuracy of NNs. The results of our proposed method save up to 24% of inference accuracy of an MNIST trained Multi-Layer-Perceptron on MTJ-based crossbars.
Original language | English |
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Title of host publication | ASP-DAC 2020 |
Subtitle of host publication | 25th Asia and South Pacific Design Automation Conference, Proceedings |
Publisher | IEEE |
Pages | 393-400 |
Number of pages | 8 |
ISBN (Electronic) | 978-1-7281-4123-7 |
ISBN (Print) | 978-1-7281-4124-4 |
DOIs | |
Publication status | Published - 2020 |
Event | 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) - Beijing, China Duration: 13 Jan 2020 → 16 Jan 2020 Conference number: 25th |
Conference
Conference | 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) |
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Country/Territory | China |
City | Beijing |
Period | 13/01/20 → 16/01/20 |
Keywords
- neural networks
- resistive memory
- retention