• Tim Fritzmann
  • Uzair Sharif
  • Daniel Müller-Gritschneder
  • Cezar Reinbrecht
  • Ulf Schlichtmann
  • Johanna Sepulveda

Increasingly complex and powerful Systems-on-Chips (SoCs), connected through a 5G network, form the basis of the Internet-of-Things (IoT). These technologies will drive the digitalization in all domains, e.g. industry automation, automotive, avionics, and healthcare. A major requirement for all above domains is the long-term (10 to 30 years) secure communication between the SoCs and the cloud over public 5G networks. The foreseeable breakthrough of quantum computers represents a risk for all communication. In order to prepare for such an event, SoCs must integrate secure quantum-computer-resistant cryptography which is reliable and protected against SW and HW attacks. Empowering SoCs with such strong security poses a challenging problem due to limited resources, tight performance requirements and long-term life-cycles. While current works are focused on efficient implementations of post-quantum cryptography, implementation-security and reliability aspects for SoCs are still largely unexplored. To this end, we present three contributions. First, we present a RISC-V co-processor for post-quantum security, able to support lattice-based cryptography. Second, we use HW/SW co-design techniques to accelerate the NTT transformation and hash generation. Third, we perform the fault analysis of the implementation. We show that our coprocessor achieves high reliability and security capabilities while preserving good performance.

Original languageEnglish
Title of host publication2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Subtitle of host publicationProceedings
PublisherIEEE
Pages1148-1153
Number of pages6
ISBN (Electronic)978-3-9819263-2-3
ISBN (Print) 978-1-7281-0331-0
DOIs
Publication statusPublished - 2019
Event22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy
Duration: 25 Mar 201929 Mar 2019

Conference

Conference22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
CountryItaly
CityFlorence
Period25/03/1929/03/19

    Research areas

  • HW/SW co-design, Lattice-based cryptography, NewHope, RISC-V

ID: 55512729