Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Tunnel-field-effect transistors (TFETs) operate by quantum band-to-band tunnelling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFET-based SRAM utilisation for Low STandby Power applications. An 8 T TFET SRAM cell operating at VDD = 1 V, which, in contrast to other 6 T TFET SRAMs, is write-disturb- and half-selection-free is proposed. Simulations based on 30 nm p- and n-TFETs models relying on ID, CGS, CGD vs. VGS, and VDS look-up tables
extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120 and 200 mV, respectively, which are well above state of the art values repotted in the literature. When utilised in an 128 × 128-bit memory array the proposed cell enables read and write operation at 3.84 GHz and 806 MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for Internet of Things applications.