Process variation occurring during fabrication of complex VLSI devices induce uncertainties in operation parameters (e.g., supply voltage) to be applied to each device in order for it to fit within the allowed power budget and get the optimum
power efficiency. Therefore, an efficient post manufacturing performance estimation mechanism is needed in order to tune operation parameters for each device during production. The current state-of-the-art approach of using Process Monitoring Boxes (PMBs) have shown some limitations in terms of cost and accuracy that limit their benefit. Simulation results on ISCAS'99 benchmarks using 28nm FD-SOI library show that the accuracy of PMB approaches is design dependent, and requires up to 8.20 % added design margin. To overcome those limitations, in this paper we propose an alternative solution using transition
fault (TF) test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of performance estimation. The paper discusses a case study on real silicon comparing the performance estimation using functional test patterns and the TF based approach on a 28nm FD-SOI CPU. The results show a very close correlation between TF test patterns and functional patterns.
Original languageEnglish
Title of host publication2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS)
Place of PublicationDanvers
Number of pages5
ISBN (Electronic)978-1-5090-6377-2
ISBN (Print)978-1-5090-6378-9
Publication statusPublished - 2017
Event2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Palma de Mallorca, Spain
Duration: 4 Apr 20176 Apr 2017


Conference2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
Abbreviated titleDTIS 2017
CityPalma de Mallorca

    Research areas

  • Benchmark testing, Chirp, Libraries, Measurement uncertainty, Lead

ID: 37386052