VASILE: a reconfigurable vector architecture for instruction level frequency scaling

L Petrica, V Codreanu, SD Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

6 Citations (Scopus)

Original language	English
Title of host publication	12th IEEE low voltage low power conference
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	1-4
Number of pages	4
ISBN (Print)	978-1-4673-6104-0
Publication status	Published - 2013
Event	FTFC 2013 - Piscataway Duration: 20 Jun 2013 → 21 Jun 2013

Name
Publisher	IEEE

Conference	FTFC 2013
Period	20/06/13 → 21/06/13

Cite this

@inproceedings{e05eb66f00dd426b8432eddc5205c0da,

title = "VASILE: a reconfigurable vector architecture for instruction level frequency scaling",

author = "L Petrica and V Codreanu and SD Cotofana",

year = "2013",

language = "English",

isbn = "978-1-4673-6104-0",

publisher = "IEEE Society",

pages = "1--4",

editor = "s.n.",

booktitle = "12th IEEE low voltage low power conference",

note = "FTFC 2013 ; Conference date: 20-06-2013 Through 21-06-2013",

}

TY - GEN

T1 - VASILE: a reconfigurable vector architecture for instruction level frequency scaling

AU - Petrica, L

AU - Codreanu, V

AU - Cotofana, SD

PY - 2013

Y1 - 2013

UR - http://ce-publications.et.tudelft.nl/publications/1367_vasile_a_reconfigurable_vector_architecture_for_instructio.pdf

M3 - Conference contribution

SN - 978-1-4673-6104-0

SP - 1

EP - 4

BT - 12th IEEE low voltage low power conference

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

T2 - FTFC 2013

Y2 - 20 June 2013 through 21 June 2013

ER -